Makefile print variable. Apr 27, 2006 · make -pns (chortle) prints out variables and macros. Jun 19, 2017 · put a . Nov 17, 2009 · m for information during makefile remakes. Computed variable names are an advanced concept, very useful in more sophisticated makefile programming. I have a Makefile target, in which I have to check the value of an environment variable. In simple situations you need not consider them, but they can be extremely useful. in your directory where the Makefile is installed; from now running make will use your environment variables; I used this to test. Makefile: all: echo "Hello ${FOO}" . It is not portable to other versions of make. If you want to do the redirection from within the Makefile, you can invoke make recursively from a special target based on some variable being set (or not set). Here is a table of automatic variables: $@. Jun 9, 2016 · mytest: printf 'Now time is %s\n' "$$(date --iso=seconds)" where the double dollar sign escapes the dollar sign from Make so that you pass through a command substitution to the shell. See examples of how to use $*, $($*), and $(origin) functions to debug your Makefiles. Chapter 12. Basically the idea is to use addprefix and addsuffix to add quotes at the beginning and at the end of each word in L_PATH_INCLUDE. In order to create the directory only when out. 23 Printing variable from within Makefile. Variables may be referenced inside the name of a variable. ) Aug 31, 2018 · 20. Steps: run make test setting env: export TEST_ENV_ONE=OneString. 81 or higher, $(info) is available. Improve this answer. It is handled directly by make: no shell is invoked. As for $(id -u), you need to duplicate the dollar $$, otherwise Make thinks it's a Make variable access, and replaces it with an empty string there's there's no such variable. That's what $< expands to. g. For example: clean: @if [ "test" = "test" ]; then\. > make list. Instead, to force immediate expansion, you will have to create another variable with makefile-specific name (i. Stop. h gcc -c $< -o $@ Here, hello. (If the ‘ -e ’ flag is specified, then values from the environment override assignments in the makefile. too. make: *** No targets. To substitute a variable’s value, write a dollar sign followed by the name of the variable in parentheses or braces: either ‘ $ (foo) ’ or ‘ $ {foo} ’ is a valid reference to the variable foo. run another program, that can read TEST_ENV_ONE. echo "Hello world";\. Jul 6, 2021 · This might be tedious but you could go to each makefile and echo the makefile's location and filename. This is achieved by prefixing the variable with $@_. Reading another makefile (see section Including Other Makefiles). Nov 5, 2019 · How to print out a variable in makefile. Mar 23, 2016 · There does exist a variable containing the target names that were specified at the command line: MAKECMDGOALS. to get the value of X once for each variable you are interested in. Feb 2, 2011 · Running make with the following Makefile will instantly exit: a = $(shell sleep 3) Running make with the following Makefile will sleep for 3 seconds, and then exit: a := $(shell sleep 3) In the former Makefile, a is not evaluated until it's used elsewhere in the Makefile, while in the latter a is evaluated immediately even though it's not used. Debugging Makefiles. foo = some_file. Related questions. ONESHELL special target) but not very nice. May 17, 2011 · 2 Answers. Nov 23, 2016 · I want to assign variables in foreach loop based on some condition. Example makefile: DEBUG := $(filter test,$(MAKECMDGOALS)) all: @echo all : $(MAKECMDGOALS) : $(DEBUG) : $(if $(DEBUG),1,0) To print the data base without trying to remake any files, use ‘make -qp ’. ? Bonus: Why does the removal of ifdef result in Makefile:3: *** missing Appendixes. json define my_func file=$ Aug 29, 2012 · I have a makefile where I want to read module name from input and then make directory based on it`s name. c -o hello +1 for showing the variations; the short of it: (a) $(shell ) only sees variables that were already present in make's own environment when it started; (b) defining variables on make's command line overrides definitions of the same name inside the makefile. You can write a common "printing" rule like this (seen in GMSL): print-%: @echo value of "$*" is "$($*)" And then just do make print-libdir. The first dependency is hello. o is the output file. Instead, most debugging is performed with simple print statements and by inspection of the makefile. Unfortunately, there is no such thing as a makefile debugger to examine how a particular rule is being evaluated or a variable expanded. all : @echo $(Foo) "inherit to be reused by code that uses the base class, not to reuse base class code", Sutter and Alexandrescu, C++ Coding Standards. Keep in mind that, if your file contains $ signs, MAKE will try to expand them as variables/directives when my_variable is expanded (or when assigned, of you define it with :=). The following example takes the n-th file from SRC / OBJ and processes them together. (The default for INSTALL_PROGRAM should be $(INSTALL); the default for INSTALL_DATA should be ${INSTALL} -m 644 . These variables are defined in the sub-make as defaults, but do not override what is specified in the makefile used by the sub-make makefile unless you use the `-e' switch (see section Summary of Options). Version $(VERSION) of $(PACKAGE_NAME) has been released. pax@paxbox> touch a b ; make. Just combine the commands in one line, separated by commas, use double dollars; if the line is long, escape the new lines. The data base output contains file name and line number information for recipe and variable definitions, so it can be a useful debugging tool in complex environments. I have (kind of) specific use-case where I need to do these steps: run command1. Nov 11, 2016 · Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. An obvious solution is to just have . Tried hard, but can't find it. You don't say so specifically but because of the syntax I'll assume you're using GNU make. A sequence of lines like this is considered a Aug 6, 2015 · 34. In GNU Make 3. I have one rule that creates some dynamically generated variables and assigns variables to them, then passes those variables along to a call to build a separate rule. Mar 30, 2015 · Make can read a makefile from stdin, so you can give it a here document that is a makefile. c another_file. Aug 22, 2012 · Stack Overflow Public questions & answers; Stack Overflow for Teams Where developers & technologists share private knowledge with coworkers; Talent Build your employer brand Include another makefile. $(eval $(shell echo OUTPUT_RC=`whoami`; echo $$?)) How to assign the output of a Aug 7, 2016 · If you have one makefile including another in a different directory, PWD and CURDIR aren't updated for the child makefile. Environment variable name: TEST, its value: "TRUE". So, in your makefile, you can set a make variable, and then pass it to the gcc command line options. That's a sh quirk (a shell Make uses by default), not a make quirk. Say I have this Makefile. (This is because make interpret each line as a seperate command unless it ends with \) edited Jul 26, 2021 at 7:53. The file name of the target of the rule. GNU make supports some variables that have special properties. It can appear anywhere in a makefile, not just in a recipe. Using the special rule shown above it's possible to type commands like. run command3 which read env variable assigned in step 2. If that second makefile needs to know where it is, the following will tell you. Sorted by: 44. If this file name was /bin/make, then the recipe executed is ‘ cd subdir && /bin/make ’. However, if I add a rule, it works: x = foo bar baz ifdef x t: @echo $(x) endif Is it really necessary to add rules for outputting variables for debugging, etc. Again, to be clear: "make -d" is not a solution. To circumvent this issue, one can use the target functionality to model a loop. make -n. *:'. If you are writing to a log file, you don't want the log file name to change every time you access it in a single make command. . Contains the name of each makefile that is parsed by make, in the order in which it was parsed. See The override Directive. Command line. $ make help. 60 gnu make: list the values of all variables (or "macros") in Moreover, if one of the original . touch c. @echo 'no toto around'. var, whose recipe will output the value of the given make variable. Check out $(origin) function. However in Ubuntu, /bin/sh is provided by Dash, which supports this feature. export variable export Jun 17, 2014 · Variables specified on make command line override the values assigned in makefile: TMPDIR := "/tmp". (You can, however, use a variable reference in the name if you want the name not to be a constant. VAR='foo'. myrule: mycommand but then call make myrule > logfile. Here is another post that goes more into detail with printing variables. ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile And if I run this command directly in the console, and directly where my makefile is: Instead, text is expanded and the resulting message is displayed, but processing of the makefile continues. To print the data base of predefined rules and variables, use ‘make -p -f /dev/null’. ‘-q’ ¶ Sep 1, 2017 · You need to remove the dollar around toto, and also pass toto from the command line differently. You can alter the values of these variables in the makefile, with arguments to make, or in the environment to alter how the implicit rules work without redefining the rules themselves. show commands executed the next run of make: make --dry-run. Define a variable, overriding any previous definition, even one from the command line. For example, in this makefile: Mar 16, 2009 · Yes, you can use the define keyword to declare a multi-line variable, like this: define ANNOUNCE_BODY. No makefile name or line number is added. make print-TRICK_SFLAGS. As a special feature, using the variable MAKE in the recipe of a rule alters the effects of the -t (--touch), -n (--just-print), or -q (--question) option. In that case you can use the . If the target is an archive member, then ‘ $@ ’ is the name of the archive file. VARIABLES was modified in your makefile, the two most voted answers won't catch it. test: @echo $(TMPDIR) And then: make TMPDIR=whatever. It will give you a list of the defined targets. resulting in a variable FOOBAR in your Makefile. make print-TRICK_CFLAGS. Oct 10, 2016 · Also it shows that using a variable with single dollar (${LINE}) just gives you a blank (because the makefile doesn't interpret it as a shell variable). A variable is a name defined in a makefile to represent a string of text, called the variable’s value. A directive is an instruction for make to do something special while reading the The recipes in built-in implicit rules make liberal use of certain predefined variables. If the FLAGS are omitted, then the behaviour is the same as if -d was specified. c. If you just do the obvious thing of using "echo Accessing shell variables. A variable definition is a line that specifies a text string value for a variable that can be substituted into the text later. It is generally considered a bad practice for makefiles to depend on environment variables because that may lead to non-reproducible builds. ZS=$(Z)$(S) S=s. e. So libdir:=${libdir} and make -np will produce the desired result. As you use GNU make we could also use abspath and create temporary files named $(TAGSDIR)/$(abspath $@) but I do not know what abspath does under Windows with drive letters, nor do I know if you can name a file something\c:\something Aug 26, 2020 · I have a simple Makefile where I want to pass a list of files and store them inside a variable in user-defined function and print the file names. Deciding (based on the values of variables) whether to use or ignore a part of the makefile (see section Conditional Parts of Makefiles). For example: $(info Serial result = $(S_RES)) If your make 's version is 3. Variable values of the top-level make can be passed to the sub-make through the environment by explicit request. Mar 6, 2015 · Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. The argument to the eval function is expanded, then the results of that expansion are parsed as makefile syntax. Anyway, I made little hack to extract the targets from a makefile, which you can include in a makefile. The simple makefile example shows a variable definition for objects as a list of all object files (see Variables Make Makefiles Simpler). Sep 29, 2009 · If the assignment depends on the loop-variable, VAR will be empty. Assignments to variables on the command line override the values from the makefile. The tricky part is getting your multi-line variable back out of the makefile. c:a b. Assuming you have GNU make, you can use the shell function to run the first command and save its output in a Make variable. make -Bn. Aug 16, 2016 · If you use a special version of make to run the top-level makefile, the same special version will be executed for recursive invocations. all: It sets five variables: X, Y, Z, S, YS, and ZS. my_test: ifdef toto. Every Makefile should define the variable INSTALL, which is the basic command for installing a file into the system. Using this construction you can even use $(eval ) to process the loop variable, as demonstrated with VAR3 The eval function is very special: it allows you to define new makefile constructs that are not constant; which are the result of evaluating other variables and functions. assign output form command2 to env variable. make: 'c' is up to date. Is there something I can put in the Makefile. else. fi. These values are substituted by explicit request into targets, prerequisites, recipes, and other parts of the makefile. Variable names are usually chosen to be in all capital letters for clarity. Lines in the rule's recipe are passed to the shell for handling, they're not parsed by make (except to expand variable/function references). However, there is a special feature of GNU make , secondary expansion (see Secondary Expansion ), which will allow automatic variable values to be used in prerequisite lists. tar are evaluated. mk, but i don't get the console echo. If you want to avoid it, you need to escape them Dec 19, 2013 · At the moment, I'm able to check the Makefile variable, and then as part of my target specific rules, write shell commands that prompt the user for the password and store it in a shell variable. Note that it doesn't include the default target if it wasn't explicitly specified at the command line. ifdef build. override variable-assignment. all: @echo build has the value $(build) Note the usage of := as opposed to =. Although not too important in this example, it is useful to understand the difference. 1 Splitting Recipe Lines. A variable is a name defined in a makefile to represent a string of text, called the variable's value. 6. VARIABLES)) Note, that make target BLABLBAH=toto does not create an "external variable" (that term is not well-defined so I'm just guessing that by this you mean variables Apr 20, 2019 · However simple variables are immediately expanded. gmake print-X. All exported shell environment variables are accessible like so: $(MYBASEDIR) Example. Jun 11, 2021 · This results in Makefile:4: *** commands commence before first target. mytarget: $(eval $@_foo = bar) @echo mytarget: $($@_foo) other: mytarget @echo other: $($@_foo) Dec 24, 2016 · Every line in a makefile (that appears after a rule statement) that is indented with a TAB character is part of the rule's recipe. So that line could be skipped. names of such variables should be different in each makefile): Jun 26, 2021 · IN addition to the answer below: You don't need to use absolute paths in most of these cases and if you do it's preferrable to use CMAKE_CURRENT_SOURCE_DIR, since this refers to the directory containing the current CMakeLists. 80 or lower, $(warning) might meet the purpose. The expanded results can define new make variables, targets Jul 10, 2010 · The $@ and $< are called automatic variables. How to print out a variable in makefile Jul 19, 2023 · To not print -e, just remove it from the command. edited Nov 24, 2022 at 21:44. edited Apr 19, 2019 at 16:17. This special significance of ‘ $ ’ is why you must write ‘ $$ ’ to have the effect of a single 2. They are words to which a string of characters can be assigned. 14 Other Special Variables. for example I have a messy tcl script for evaluating all variables using make -pns so for a makefile: Code: AA = ${PWD} AAA = ${AA} all: Feb 26, 2023 · A variable definition is a line that specifies a text string value for a variable that can be substituted into the text later. However, an explicit assignment in the makefile, or with a command argument, overrides the environment. 1. (If the ‘-e’ flag is specified, then values from the environment override assignments in the makefile. So you can do (from bash): FOOBAR=1 make. Every Makefile should also define the variables INSTALL_PROGRAM and INSTALL_DATA. The following is a makefile that includes your kernel makefile and adds a new wildcard target, %. @echo 'toto is defined'. Dec 12, 2017 · If you are going to use eval anyway, make it print things you can eval directly. Apr 14, 2021 · You can use eval to set variables in a recipe. Our examples show C programs, since they are very Apr 24, 2006 · I am wondering which command is used for print out variable value in Makefile. Thus, if the first thing a makefile does is examine the last word in this variable, it Aug 2, 2013 · The problem is that if I print HEADER in my makefile using: print: @echo $(HEADER) I get . You should export the variable using Make’s constructs: export SOME_ENV := someTest test: go test or specify the variable inline: test: SOME_ENV=someTest go test or ensure both lines are run in the same shell: test: export SOME_ENV=someTest && \ go test Mar 1, 2019 · It is a default behaviour of make to print both the command and its output to stdout. am to cause it to print out the value of the variable: E. /mod Aug 22, 2018 · The simplest way to define a variable in a makefile is to use the = operator. Jan 26, 2019 · CSRC:= $(foreach dir,$(SRCDIR),$(wildcard $(dir)/*)) If you look at the documentation: $(wildcard pattern…) This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match one of the given file name patterns…. If you want to suppress echoing the output, use the "@" sign. This is the makefile implementing the steps described above. If simple space instead of escape sequence \t is allowed, and your make is GNU make 3. For example: hello. This target filters out and prints all the variables that were defined in a makefile: print_file_vars: $(foreach v, $(. You can cancel all variables used by implicit rules with the ‘ -R Nov 18, 2017 · info is a GNU make function. Apr 18, 2018 · If we add these lines to the top level sim makefile. How Variables Get Their Values Oct 15, 2020 · So, you need to look elsewhere to find out why this is not working for you. endef. – Mar 18, 2024 · One of the features of a Makefile is that it enables the use of variables, i. Using the MAKE variable has the same effect as using Sep 2, 2013 · Some of the files are not being compiled, which I suspect is a problem with one of the variables being incorrect. Variable Works. To give a quick overview, you can do gcc -DSYMBOL=1, and this would result in the compiler adding this to the code: #define SYMBOL 1. txt file regardless of whether there's a project() command or not; in more complex projects you may leave out this command in a subdirectory. env: FOO=alex In your example, the TMP variable is set (and the temporary directory created) whenever the rules for out. $(info build has been defined) endif. Dec 28, 2015 · No, you cannot "see" the full list of arguments of the make command in a Makefile. export. You can just replace echo with your command and it'll do it. LOGPATH = logs. o: hello. ) The result of this function is a string containing the value of variable, without any expansion occurring. Alternatively, you can set all those variables to its default values in the makefile. Go to the first, previous, next, last section, table of contents . However, warning prints line number etc. How to Use Variables. One of the few ways in which make does interpret recipes is checking for a backslash just before the newline. Then you can go on to print when a variable was defined as the makefile runs. As in normal makefile syntax, a single logical recipe line can be split into multiple physical lines in the makefile by placing a backslash before each newline. Note that the closing ; and \ at each line are necessary. Update: This is not possible according to accepted answer with comments. VARIABLES special variable: $(info Variables: $(. The following one can print the message, but it will not execute the script after it. tar : $(eval TMP := $(shell mktemp -d)) @echo hi $(TMP)/hi. VARIABLES), $(if $(filter file,$(origin $(v))), $(info $(v)=$($(v))))) Z=cat. See Communicating Variables to a Sub-make. Because no shell is invoked, there are no quoting issues. If you copy/paste my answer in your Makefile, please be aware of replacing the four spaces by a proper Note that this variable should be used only in special circumstances. Using Bash arithmetic expansion: echo $$(( $(JPI) * $(JPJ) )) The first line is to choose the Bash shell instead of the default (sh). c hello. make toto=1 my_test. See Including Other Makefiles. Learn how to use a simple Makefile recipe to print the value and origin of any variable in your Makefile. , placeholders for values that we can alter. whatever. Recursive make commands should always use the variable MAKE , not the explicit command name ‘ make ’, as shown here: subsystem: cd subdir && $(MAKE) The value of this variable is the file name with which make was invoked. Jul 4, 2012 · I need to create a variable with spaces in my Makefile: CC=$(LFS_TGT)-gcc -B$(TOOLS)/release/lib/ What is a right way to do that? UPDATE: My code does not work, I have an error, something like Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. env files; run direnv allow . However, because info is a make function it is parsed by make before the shell is invoked: that Sep 20, 2021 · I am trying to figure out how to use env variables in makefiles. $(info text…) ¶ This function does nothing more than print its (expanded) argument(s) to standard output. etc, etc. In case you want to see all commands (including the compiled ones) of the default target run: make --always-make --dry-run. here is my code: build: @read -p "Enter Module Name:" module; module_dir=. Debugging makefile s is somewhat of a black art. Moreover, we can define and reference variables in a Makefile: $ (name) Alternatively, we can use {}: $ {name} In this case, name is the name of the variable. test_target: ifeq ($(TEST),"TRUE") echo "Do something". Jun 10, 2023 · rule: echo In makefile $(current_makefile): echo Making target $@ it will always print the name of the root makefile. Which is essentially the same thing as (the more common and shorter): $ INTEGRATION=true make help. txt. Typically, sh doesn't support arithmetic expansion. These values are substituted by explicit request into targets, prerequisites, commands, and other parts of the makefile. The name is appended just before make begins to parse the makefile. Once a string has been assigned to the variable, every reference to the variable in the rest of the makefile is replaced by the string. tar is actually fired, you need to move the directory creation down into the steps: out. It looks like make --debug=b is the best option for what you need, as shown in the following transcript: pax@paxbox> cat makefile. awsecrpush: VAR := $(shell sudo echo "ls -lah") sudo -s $(VAR) Share. It can be downloaded from $(DOWNLOAD_URL). list: copy: Nov 28, 2015 · You need to use the $ (shell operation) command in make. You can see the list of "targets" in the order they were entered on the command line, e. The manual describes the GNU implementation of make, which was written by Richard Stallman and Roland McGrath, and is currently maintained by Paul Smith. build:=1. For example, to assign the command gcc to a variable CC: CC = gcc This is also called a recursive expanded variable, and it is used in a rule as shown below: hello: hello. GNU make - How to Use Variables. 5. The result of the expansion of this function is the empty string. For example in practice I want to use it for going through all required tools (gcc g++ as ld) check if they are found on system path. This way the user have to specify the values of those variables only if the defaults are not suitable. It's just a start - it doesn't filter out the dependencies, for instance. Just to point out the obvious, it is unfortunate that Make uses a syntax which is so similar to the shell's command substitution syntax. You are free to choose a target other than the default in this example. Jan 24, 2017 · c:\dir1\include C:\dir2\include C:\dir3\include. Defining a variable from a verbatim string containing multiple lines (see section Defining Variables Verbatim). Sep 22, 2021 · This is doable with a shell variable and a one-line recipe (or the . But other way it's not possible. Apr 27, 2014 · I want to print some message while doing build process with a makefile. list: @grep '^[^#[:space:]]. Note that you don't need to put the $(info) in a recipe; For example here's a one line makefile printing an environment variable: Makefile: $(info VAR='$(VAR)') Set the environment variable VAR and run make: $ VAR=foo make. $(dir $(realpath $(lastword $(MAKEFILE_LIST)))) MAKE. But, I don't get the exact syntax of it. 80 the authors introduced a couple of new features that make it feasible to print out the value of This example defines the variables `dir', `foo_sources', and `foo_print'. env file in your directory and put your variables there; install and setup direnv for your shell configure it to allow . To print the data base without trying to remake any files, use ‘make -qp ’. From this answer here, I understand that you can even create pseudo local variables that way, by automatically prefixing them with the target. e. This will let you print environment variables and makefile variables from the command line. Jun 13, 2009 · --debug[=FLAGS] Print debugging information in addition to normal processing. BTW. The make utility will determine automatically which pieces of a large program need to be recompiled, and issue the commands to recompile them. You must have a rule, in order to have some shell code executed: For instance: Code: Foo=newdir. FLAGS may be: 'a' for all debugging output same as using -d, 'b' for basic debugging, 'v' for more verbose basic debugging, 'i' for showing implicit rules, 'j' for details on invocation Jul 22, 2019 · That's somewhat more flexible in that you might not need to worry so much about subshells. (set the variable in the shell, so all subsequent commands can see it until you un-export it again), or you can use: $ env INTEGRATION=true make help. Makefile. c ${CC} hello. Any help is appreciated. REQUESTS:=request/*. ‘-q’ ¶ Of course, you can avoid using shell and a temporary file if you can explicitly write file contents for Makefile usage. If you use operation, then the shell command will get evaluated every time. Note that nested variable references are quite different from recursively expanded variables (see section The Two Flavors of Variables), though both are used together in complex ways when doing makefile programming. Tell make to export all variables to child processes by default. 1 Basics of Variable References. The variable $@ represents the name of the target and $< represents the first prerequisite required to create the output file. I am trying to set an Environment variable in a Makefile, so it can be used in another program running in the sam shell as make, but after make has run. A directive is an instruction for make to do something special while reading the Jun 20, 2014 · I'm trying to put together some complicated makefile rules to automate building a project against multiple compilers. $ cat Makefile all: @echo $(FOO) Now with no variable set, big surprise, we get nothing: $ printenv | grep FOO $ $ make $ With the variable just set, but not exported: Feb 29, 2012 · LOCAL_PATH := $(call my-dir) all:;echo $(LOCAL_PATH) echo: $(LOCAL_PATH) print:echo "i'm not working" When i do ndk-build, just compile all the Android. LOGFILE = $(LOGPATH)/$(shell date --iso=seconds) Jun 30, 2021 · and the latter doesn’t see the environment variable. This is what $@ expands to. Jan 13, 2021 · You can either use: $ export INTEGRATION=true. This means your original line actually reads as: CSRC := $(wildcard src1/ src2 Jan 15, 2019 · In this case, echo is additionally executed inside a recipe, which is where it is used most of the time. However, this variable is only available to that specific shell and not any others. c print_out_something_helpful($(foo)) Aug 24, 2012 · Therefore you would not normally use a ‘$’ or parentheses when writing it. pax@paxbox> make. If you are gcc or, any similar compiler, you can use the -D flag, documented inside the manpage. print-% : @echo '$*=$($*)'. This is called a computed variable name or a nested variable reference. I have readed the GNU make info (ndk-build is just a tiny GNU make), and some post whom said echo must work using a $(VAR) but it's not working on my case. Variables in a makefile work much the same as variables in a shell script. ms vx cw wz xa gm yx ea zi ac